The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device that includes a static random access memory.
A static random access memory (referred to hereinafter as SRAM) is a high-speed semiconductor memory device including a transfer transistor selected by a word line and two CMOS inverters forming together a flip-flop connection, wherein each of the CMOS inverters is connected to a corresponding bit line via a corresponding transfer transistor. SRAMs are used extensively in high-speed logic circuit devices together with high-speed logic elements such as CMOS circuit.
FIG. 1 is an equivalent circuit diagram of a typical SRAM 10.
Referring to FIG. 1, the SRAM 10 includes a first CMOS inverter I1 in which a first load transistor LT1 and a first driver transistor DT1 are connected in series, a second CMOS inverter I2 in which a second load transistor LT2 and a second driver transistor LD2 are connected in series. The first CMOS inverter I1 and the second CMOS inverter I2 form together a flip-flop circuit FF, wherein a node N1 connecting the first load transistor LT1 and the first driver transistor DT1 with each other, is connected to a first bit line BL via a first transfer transistor TF1, while the first transfer transistor TF1 is controlled by a word line WL. Similarly, a node N2 connecting the second load transistor LT2 and the second driver transistor DT2 with each other, is connected to a first bit line /BL via a second transfer transistor TF2 controlled by the word line WL.
In SRAMs of such a construction, current drivability of the load transistors LT1 and LT2 that drive the driver transistors DT1 and DT2 is extremely important for attaining high-speed operation of the SRAM.    Patent Reference 1 Japanese Laid-Open Patent Application 2006-41035    Patent Reference 2 Japanese Laid-Open Patent Application 7-131003    Patent Reference 3 Japanese Laid-Open Patent Application 7-169858    Patent Reference 4 Japanese Laid-Open Patent Application 2002-329798    Patent Reference 5 Japanese Laid-Open Patent Application 2002-190534